Recently, there has been proposed a Resistive RAM (ReRAM) that uses variable resistive elements, which reversibly change a resistance value, as a memory. This ReRAM includes the variable resistive element between a sidewall of a word line extending parallel to a substrate and a sidewall of a bit line extending perpendicular to the substrate. This structure ensures further highly integrated memory cell array. With the memory cell array with such structure, a selection gate transistor is coupled to a lower end of the bit line. This selection gate transistor selectively couples each of the bit lines to a global bit line.